Viterbi Decoding with Dual Timescale Traceback Processing

نویسندگان

  • Olaf J. Joeressen
  • Heinrich Meyr
چکیده

In this paper a new approach to traceback processing in Viterbi decoders is presented. The approach reduces memory requirements as compared to previous approaches by using di erent speeds during acquisition of the best trellis path and the subsequent decoding of a block of data. This dual timescale approach allows in-place updating of the stored information and nicely matches the constraints of commodity semi-custom technologies.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Study of Viterbi Decoder Algorithm for Wireless LANs

Viterbi Decoders are commonly used to decode convolutional codes in communications systems. This Viterbi Decoder is a fully parallel implementation which gives fast data throughput. The decoder is targeted for WiMAX and Wireless LAN applications. Input symbol metric pairs are decoded into output data bits by the maximum likelihood Viterbi processor core. Decoder supports both hard and soft inpu...

متن کامل

A Low Power Viterbi Decoder Design with Minimum Transition Hybrid Register Exchange Processing for Wireless Applications

This work proposes the low power implementation of Viterbi Decoder. Majority of viterbi decoder designs in the past use simple Register Exchange or Traceback method to achieve very high speed and low power decoding respectively, but it suffers from both complex routing and high switching activity. Here simplification is made in survivor memory unit by storing only m-1 bits to identify previous ...

متن کامل

A Vlsi Implementation of an Adaptive-effort Low-power Viterbi Decoder for Wireless Communications

Low-power error-correction is required for 3rd generation digital wireless devices. Adaptive-reduced state sequence detection (A-RSSD) modifies a Viterbi decoder to use far less computational effort than is typical. RSSD neglects the oldest p bits of the encoder's state machine, treating the code as if it were of length K' = K-p. Through successive reduction of p, decoding can proceed with more...

متن کامل

Architectural tradeoffs for survivor sequence memory management in Viterbi decoders

In a Viterbi decoder, there are two known memory organization techniques for the storage of survivor sequences from which the decoded information sequence is retrieved, namely register exchange method and traceback method. This paper extends previously known traceback approaches describes two new traceback algorithms, and compares various traceback methods with each other. Memory size, latency ...

متن کامل

Hardware Implementation and performance evaluation of Viterbi Decoder using Parallel decoding approach over Xilinx Virtex-6 FPGA

The wide spread use of computers and communication devices in every aspect of life demands the data transmission to be reliable as well as secure. Different design procedures and algorithms are being designed to overcome the security and reliability issues related to transmission of electronic information. Convolutional encoding with Viterbi algorithm is one of the most powerful forward error c...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2007